Semiconductor memory device and manufacturing method therefor

ABSTRACT

First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2009-003857, filed Jan. 9, 2009,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amanufacturing method therefor, for example, a NAND flash memoryincluding a selection gate transistor.

2. Description of the Related Art

A NAND flash memory has a NAND string in which a drain-side selectiongate transistor and a source-side selection gate transistor are arrangedat both ends of memory transistors connected in series with each other.The drain-side selection gate transistor is connected to a bit linethrough a bit line contact electrode. The source-side selection gatetransistor is connected to a source line through a source line contactelectrode. The NAND strings are arranged in a direction orthogonal to adirection in which memory cells are connected in series with each other.Adjacent NAND strings are arranged such that drain-side selectiontransistors of the NAND strings are adjacent to each other orsource-side selection transistors of the NAND strings are adjacent toeach other.

A method of manufacturing a conventional NAND flash memory is describedin Jpn. Pat. Appln. KOKAI Publication No. 2002-231832.

In this manufacturing method, if a space between a memory celltransistor and a selection gate transistor adjacent thereto (spacebetween MG and SG1) and a space between adjacent selection gatetransistors (space between SG1 and SG2) are larger than a space betweenthe adjacent memory transistors (space between MG and MG) each, halo ionimplantation is consequently performed at a high concentration betweenMG and SG1 and between SG1 and SG2. As a result, a threshold voltage ofthe memory cell transistor arranged adjacent to the selection gatetransistor disadvantageously excessively rises.

Aside from this, on a semiconductor substrate on which the memory celltransistors and the selection gate transistors are formed, a peripheralcircuit including a peripheral transistor is formed.

A semiconductor memory device in which a film thickness of a sidewallinsulating film of the peripheral transistor is larger than a filmthickness of a sidewall insulating film of the memory cell transistor isdisclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-197308.

However, when the sidewall insulating film formed between the adjacentselection gate transistors (between SG1 and SG2) increases, a contactelectrode connected to a bit line is disadvantageously brought intocontact with the sidewall insulating film. In order to avoid this, thespace between SG1 and SG2 must be increased. In this case, the length ofthe NAND bell increases, and, consequently, a chip areadisadvantageously increases.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda semiconductor memory device comprising: first gate electrodes of aplurality of memory cell transistors formed on a semiconductor substratein series with each other; a second gate electrode of a first selectiongate transistor which is adjacent to one end of the plurality of firstgate electrodes formed in series with each other and formed on thesemiconductor substrate; a third gate electrode of a second selectiongate transistor which is adjacent to the second gate electrode of thefirst selection gate transistor and formed on the semiconductorsubstrate; a fourth gate electrode of a peripheral transistor formed onthe semiconductor substrate; a first sidewall insulating film formed ona side surface of the second gate electrode; a second sidewallinsulating film formed on a side surface of the third gate electrode;and a third sidewall insulating film formed on a side surface of thefourth gate electrode. A film thickness of the third sidewall insulatingfilm is larger than film thicknesses of the first sidewall insulatingfilm and the second sidewall insulating film. A space between the firstgate electrode and the second gate electrode is larger than a spacebetween the first gate electrodes, and a space between the second gateelectrode and the third gate electrode is larger than the space betweenthe first gate electrode and the second gate electrode.

According to a second aspect of the present invention, there is provideda method of manufacturing a semiconductor memory device comprising:forming a plurality of first gate electrodes of a plurality of memorycell transistors, a second gate electrode of a first selection gatetransistor, and a third gate electrode of a second selection gatetransistor on a semiconductor substrate, the plurality of first gateelectrodes being arranged at predetermined spaces in series with eachother, the second gate electrode being arranged at one end of theplurality of first gate electrodes arranged in series with each other,and the third gate electrode being arranged adjacent to the second gateelectrode; covering the plurality of first gate electrodes, the secondgate electrode, and the third gate electrode with a first insulatingfilm, and forming the first insulating film on the semiconductorsubstrate; forming a second insulating film on the first insulatingfilm; forming a mask material on the second insulating film to cover agap between the first gate electrodes and to form a opening between thefirst gate electrode and the second gate electrode and between thesecond gate electrode and the third gate electrode; after the maskmaterial is formed, removing the second insulating films between thefirst gate electrode and the second gate electrode and between thesecond gate electrode and the third gate electrode; after the maskmaterial is removed, covering the plurality of first gate electrodes,the second gate electrode, and the third gate electrode with a thirdinsulating film, and forming the third insulating film on thesemiconductor substrate; and etching the third insulating film byanisotropic etching to form sidewall insulating films on a side surfaceof the first gate electrode between the first gate electrode and thesecond gate electrode and on side surfaces of the second and third gateelectrodes.

According to a third aspect of the present invention, there is provideda method of manufacturing a semiconductor memory device comprising:forming a plurality of first gate electrodes of a plurality of memorycell transistors, a second gate electrode of a first selection gatetransistor, a third gate electrode of a second selection gatetransistor, and a fourth gate electrode of a peripheral transistor on asemiconductor substrate, the plurality of first gate electrodes beingarranged at predetermined spaces in series with each other, the secondgate electrode being arranged at one end of the plurality of first gateelectrodes arranged in series with each other, and the third gateelectrode being arranged adjacent to the second gate electrode; coveringthe plurality of first gate electrodes, the second gate electrode, thethird gate electrode, and the fourth gate electrode with a firstinsulating film, and forming the first insulating film on thesemiconductor substrate; forming a second insulating film on the firstinsulating film; forming a mask material on the second insulating filmto cover a gap between the first gate electrodes and the fourth gateelectrode and to form a opening between the first gate electrode and thesecond gate electrode and between the second gate electrode and thethird gate electrode; after the mask material is formed, removing thesecond insulating films between the first gate electrode and the secondgate electrode and between the second gate electrode and third gateelectrode; after the mask material is removed, covering the plurality offirst gate electrodes, the second gate electrode, the third gateelectrode, and the fourth gate electrode with a third insulating film,and forming the third insulating film on the semiconductor substrate;and etching the third insulating film by anisotropic etching to formfirst sidewall insulating films on a side surface of the first gateelectrode between the first gate electrode and the second gate electrodeand on side surfaces of the second and third gate electrodes and to forma second sidewall insulating film on a side surface of the fourth gateelectrode.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a layout diagram showing a configuration of a NAND flashmemory according to a first embodiment of the present invention.

FIG. 2 is a sectional view along line 2-2 in FIG. 1.

FIGS. 3, 4, 5, 6A and 6B are sectional views showing a method ofmanufacturing the NAND flash memory according to the first embodiment.

FIG. 7 is sectional view showing a structure of a NAND flash memoryaccording to a second embodiment of the present invention.

FIGS. 8, 9A and 9B are sectional views showing a method of manufacturingthe NAND flash memory according to the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor memory device according to an embodiment of the presentinvention will be described below with reference to the accompanyingdrawings. In this case, as the semiconductor memory device, a NAND flashmemory will be exemplified. In the explanation, common reference numbersdenote common parts throughout the drawings.

First Embodiment

A NAND flash memory according to a first embodiment of the presentinvention will be described below.

FIG. 1 is a layout diagram showing a configuration of the NAND flashmemory according to the first embodiment.

As shown in FIG. 1, NAND cell units are formed on element regions 2divided by a plurality of element isolation regions 1 extending in a bitline direction. Four memory cell transistors MC are connected in serieswith each other, a drain-side selection gate transistor STD and asource-side selection gate transistor STS are connected in series withthe four serially connected memory cell transistors MC such that sourceand drain diffusion layers are shared.

The memory cells MC aligned in a word line direction which is ahorizontal direction in FIG. 1 are connected to each other by a commoncontrol gate line (word line) 3. The drain-side selection gatetransistors STD are connected to each other by common drain-sideselection gate lines 4, and the source-side selection gate transistorsSTS are connected to each other by common source-side selection gatelines 5.

In this case, the lines are arranged to satisfy “a length (L1) betweenthe drain-side selection gate line 4 and the drain-side selection gateline 4”>“a length (L2) between the drain-side selection gate line 4 andthe word line 3”>“a length (L3) between the word line 3 and the wordline 3”. Similarly, the lines are arranged to satisfy “a length (L1)between the source-side selection gate line 5 and the source-sideselection gate line 5”>“a length (L2) between the source-side selectiongate line 5 and the word line 3”>“a length (L3) between the word line 3and the word line 3”.

To the drain-side selection gate transistor STD, a bit line connectionunit 7 configured by a first interconnect layer is connected through abit line contact electrode 6, and a bit line 9 is connected through aninterconnection contact electrode 8. To the source-side selection gatetransistor STS, a source line 11 constituted by a first interconnectlayer is connected through a source line contact electrode 10.

Four memory cell transistors MC, the drain-side selection gatetransistor STD, and the source-side selection gate transistor STSconstitute one NAND string. One NAND string is adjacent to another NANDstring through the bit line contact electrode 6 in a bit line direction.Furthermore, the NAND string is adjacent to another NAND string throughthe source line contact electrode 10 in a bit line direction. The numberof memory cell transistors MC is not limited to 4. The number may be 8,16, 32, 64, or 128.

FIG. 2 is a sectional view along line 2-2 in FIG. 1, and shows asectional structure of the NAND flash memory according to the firstembodiment. FIG. 2 shows three memory cell transistors and one selectiongate transistor in a NAND cell and a selection gate transistor ofanother NAND cell arranged adjacent to the NAND cell. Furthermore, aninterlayer insulating film, a interconnect layer, and the like formed onthe memory cell transistors and the selection gate transistor are notshown.

As shown in FIG. 2, on a semiconductor substrate (for example, p-typesilicon substrate) 21, the element regions 2 divided by elementisolation regions (not shown) are formed. A gate insulating film 22 isformed on the semiconductor substrate 21 of the element region, and agate electrode MG of a memory cell transistor is formed on the gateinsulating film 22.

Each of the gate electrodes MG is constituted by a laminate gate and hasa floating gate electrode 23, an inter-gate insulating film 24, and acontrol gate electrode 25. The floating gate electrode 23 is a chargeaccumulation layer in which charges are accumulated. On the floatinggate electrode 23, the inter-gate insulating film 24 is formed. Thecontrol gate electrode 25 is formed on the inter-gate insulating film24. The control gate electrode 25 is shared by adjacent memory cells MCsin a word line direction to serve as a word line.

Each of the memory cells MC are connected in series with each other toshare source and drain diffusion layers 26 formed in the semiconductorsubstrate 21.

The drain-side selection gate transistor is arranged at one end of thememory cells connected in series with each other. The drain-sideselection gate transistor has the gate insulating film 22 and aselection gate electrode (selection gate line) SG1, a diffusion layer27, and a bit line contact diffusion layer 28 which are formed throughthe gate insulating film 22. The diffusion layer 27 and the bit linecontact diffusion layer 28 are formed in the semiconductor substrate 21,and the diffusion layer 27 is arranged on the gate electrode MG sidethrough selection gate electrode SG1, and the bit line contact diffusionlayer 28 is arranged on an opposite side of the gate electrode MG.

Furthermore, a drain-side selection gate transistor in another NANDstring is arranged adjacent to the drain-side selection gate transistorto share the bit line contact diffusion layer 28. The drain-sideselection gate transistor similarly has the gate insulating film 22, aselection gate electrode (selection gate line) SG2, a diffusion layer(not shown), and the bit line contact diffusion layer 28.

The bit line contact electrode 6 is formed between the drain-sideselection gate transistors. A bottom surface of the bit line contactelectrode 6 is on the bit line contact diffusion layer 28. The bit linecontact electrode 6 is electrically connected to the bit line contactdiffusion layer 28.

In this case, the source and drain diffusion layers 26 is constituted bya first diffusion layer 26A and a second diffusion layer 26B. The sourceand drain diffusion layers 26 is formed at the deepest position of thesource and drain diffusion layers 26 by using boron (B) ions as impurityions. The first diffusion layer 26A adjusts a threshold value of amemory cell transistor and acts as a punch-through stopper. The seconddiffusion layer 26B functions as a source and a drain of a memory celltransistor by using, for example, arsenic (As) ions as impurity ions. Inthis case, the diffusion layer 26 serves as an n-type diffusion layer onthe basis of a relationship between impurity concentrations anddiffusion positions of the first diffusion layer 26A and the seconddiffusion layer 26B.

The diffusion layer 27 is constituted by a first diffusion layer 27A anda second diffusion layer 27B. The first diffusion layer 27A is formed atthe deepest position of the diffusion layer 27 by using, for example,boron and phosphorous ions as impurity ions. The first diffusion layer27A adjusts a threshold value of a selection gate transistor and acts asa punch-through stopper. The second diffusion layer 27B functions as asource and a drain of the selection gate transistor by using, forexample, arsenic ions as impurity ions. In this case, the diffusionlayer 27 serves as an n-type diffusion layer on the basis of arelationship between the impurity concentrations and the diffusionpositions of the first diffusion layer 27A and the second diffusionlayer 27B.

The bit line contact diffusion layer 28 is constituted by a firstdiffusion layer 28A, a second diffusion layer 28B, a third diffusionlayer 28C, and a fourth diffusion layer 28D. The first diffusion layer28A is formed at the deepest position of the bit line contact diffusionlayer 28 by using, for example, B and P ions as impurity ions. The firstdiffusion layer 28A adjusts a threshold value of a selection gatetransistor and acts as a punch-through stopper. The second diffusionlayer 28B functions as a source and a drain of the selection gatetransistor by using As or P ions as impurity ions. The third diffusionlayer 28C is formed under the selection gate electrodes SG1 and SG2 tooverlap the selection gate electrodes SG1 and SG2, and acts to controlthe threshold value of the selection gate transistor. The fourthdiffusion layer 28D uses, for example, arsenic ions as impurity ions, ispresent in a surface region of the diffusion layer 28, and has animpurity concentration higher than that of the second diffusion layer28B. The fourth diffusion layer 28D functions to decrease a contactresistance to the bit line contact electrode 6. In this case, the bitline contact diffusion layer 28 serves as an n-type diffusion layer onthe basis of a relationship between impurity concentrations anddiffusion positions of the first to fourth diffusion layers 28A, 28B,28C, and 28D.

In this case, the impurity concentrations in the diffusion layer 27 andthe diffusion layer 26 are almost equal to each other. When a spacebetween the gate electrode MG and selection gate electrode SG1 and aspace between the selection gate electrodes SG1 and SG2 are larger thanthe space between the gate electrodes MG, equal doses of impurities areimplanted by ion implantation to form the diffusion layers 26A and 27A.In this case, although area densities of impurities in implantation arenot changed, the total dose of B in the diffusion layer 27A is largerthan that in the diffusion layer 26A. By scattering by causing ions torun into the gate electrodes, the impurity concentration of B in thediffusion layer 27A is higher than that in the diffusion layer 26A. As aresult, a large number of boron (B) ions are diffused under the gateelectrode MG to increase the threshold value of the memory celltransistor MC adjacent to the selection gate electrodes SG1 and SG2.

As counter implantation in the first diffusion layer 27A, for example,phosphorous (P) ions are implanted by ion implantation. The boron (B)ions in the first diffusion layer 27A are neutralized by the phosphorousions, so that the threshold value of the memory cell transistor MCadjacent to the selection gate electrodes SG1 and SG2 are prevented fromrising. As a result, a total concentration of p-type and n-typeimpurities in the diffusion layer 26 is almost equal to that in thediffusion layer 27.

Phosphorous ions are used here because phosphorous ions can be implantedinto a deep position of the semiconductor substrate 21 since the atomicweight of phosphorous is higher than that of arsenic and can effectivelyneutralize boron ions. More specifically, the diffusion layer 27Bcontains phosphorous which is not contained in the diffusion layer 26B.Furthermore, the n-type impurity concentration in the diffusion layer 27is larger than that in the diffusion layer 26.

On side surfaces of the gate electrodes between the plurality of gateelectrodes MG and side surfaces of the selection gate electrodes SG1 andSG2, a first insulating film, for example, a high-temperature oxide(HTO) film 29 is formed. At this time, the HTO film 29 is formed to havesuch a film thickness that the HTO film 29 completely buries gapsbetween the gate electrodes MG of the memory cell transistors.

On the HTO film 29 between the plurality of gate electrodes MG, a secondinsulating film, for example, a tetraethoxysilane (TEOS) film 30 isformed. At this time, the TEOS film 30 is formed to completely bury gapsbetween the plurality of gate electrodes MG.

On the HTO films 29 on the side surfaces of the selection gateelectrodes SG1 and SG2, a third insulating film, for example, atetraethoxysilane (TEOS) film 31 is formed. In this manner, on the sidesurfaces of the selection gate electrodes SG1 and SG2, a sidewallinsulating film constituted by a laminated film including the HTO film29 and the TEOS film 31 is formed. As the materials of the secondinsulating film 30 and the third insulating film 31, the same materialmay be used, or different materials may be used. The second insulatingfilm 30 and the third insulating film 31 may have the same or differentfilm qualities.

On the side surface of the gate electrode MG between the gate electrodeMG and selection gate electrode SG1, similarly, a sidewall insulatingfilm constituted by a laminated film including the HTO film 29 and theTEOS film 31 is formed.

According to the first embodiment having the above structure, in orderto prevent punch-through caused by excessively implanting an impurityinto a diffusion layer between a memory cell and a selection gatetransistor, compensation is performed by a punch-through stopper. Forthis reason, a threshold voltage of a memory cell adjacent to theselection gate transistor can be prevented from rising.

A method of manufacturing a NAND flash memory according to the firstembodiment will be described below.

FIGS. 3 to 6B are sectional views showing a method of manufacturing aNAND flash memory according to the first embodiment. As shown in FIG. 3,on the semiconductor substrate 21, since the steps performed until gateelectrodes MG of a plurality of memory cell transistors arranged inseries with each other and selection gate electrodes SG1 and SG2 ofselection gate transistors are formed on the semiconductor substrate 21are the same as those in a conventional manufacturing method, anexplanation of the steps will be omitted.

In this case, due to the restrictions of a so-called sidewall formingprocess and lithography, as shown in FIG. 3, gate electrodes are formedto satisfy a space (L1) between SG1 and SG2>a space (L2) between MG andSG1>a space (L3) between MG and MG. Furthermore, for example, arsenicions are implanted into the semiconductor substrates 21 between MG andMG, between MG and SG1, and SG1 and SG2 by ion implantation using gateelectrodes as masks to form n-type diffusion layers 26B, 27B, and 28B.In the ion implantation performed here, arsenic ions are implanted intoa semiconductor substrate surface in a vertical direction.

As shown in FIG. 4, p-type impurity ions, for example, boron ions areimplanted into the semiconductor substrate 21 under the diffusion layers26B, 27B, and 28B by ion implantation to form the diffusion layers 26A,27A and 28A which adjust a threshold value and serve as punch-throughstoppers (halo ion implantation). In the ion implantation performedhere, boron ions are implanted into the semiconductor substrate surfacein a vertical direction. In this case, although an area density ofimpurity in implantation does not change, a total dose of boron in thefirst diffusion layer 27A is larger than a total dose of boron in thefirst diffusion layer 26A. Since a space between SG1 and SG2 and a spacebetween MG and SG1 are larger than the space between MG and MG, eventhough ions are vertically implanted into the semiconductor substratesurface, the ions do not travel exactly vertical to the semiconductorsubstrate surface. For this reason, some ions are brought into contactwith the gate electrode to cause scattering. As a result, boronconcentrations in the diffusion layers 27A and 28A between SG1 and SG2and between MG and SG1 may be higher than a boron concentration in thefirst diffusion layer 26A between MG and MG.

As shown in FIG. 5, a first insulating film, for example, the HTO film29 is formed by, for example, CVD to cover the gate electrodes MG andthe selection gate electrodes SG1 and SG2 and an upper side of thesemiconductor substrate 21, i.e., the diffusion layers 26B, 27B and 28B.At this time, the HTO film 29 is formed to have such a film thicknessthat the HTO film 29 does not completely bury gaps between the gateelectrodes MG of the memory cell transistors. In formation of the HTOfilm 29, a high-temperature long-time process which has hydrogen contentis small and a small number of trapped electric charges is used. Asilicon oxide film formed by the above process is called an HTO film inthe field of semiconductors.

Subsequently, a second insulating film, for example, the TEOS film 30 isformed on the HTO film 29 by CVD. At this time, the TEOS film 30 isformed to have such a film thickness that the TEOS film 30 completelyburies gaps between the plurality of gate electrodes MG and does notcompletely bury a gap between the gate electrode MG and selection gateelectrode SG1 and a gap between the selection gate electrodes SG1 andSG2. As described above, this condition is made possible such that space(L1) between SG1 and SG2>space (L2) between MG and SG1>space (L3)between MG and MG. In formation of the TEOS film 30, as a source gas,Si(OC₂H₅)₄, i.e., tetraethoxysilane (TEOS) is used. The silicon oxidefilm formed by using TEOS as a source gas is called a TEOS film in thefield of semiconductors.

A resist 40 is applied to the resultant structure to form openingsbetween MG and SG1 and between SG1 and SG2. In order to decrease boronconcentrations in the diffusion layers 27A and 28A between MG and SG1and between SG1 and SG2, for example, phosphorous (P) ions are implantedinto the diffusion layers 27A and 28A as counter implantation by ionimplantation. In this case, doses of phosphorous to be implanted areadjusted such that a threshold value of the memory cell transistor MCadjacent to the selection gate electrodes SG1 and SG2 is equal to athreshold value of the memory cell transistor MC. As a result, a totalconcentration of n-type and p-type impurities in the diffusion layer 26Ais almost equal to that in the diffusion layer 27A.

Furthermore, boron ions are implanted into only the semiconductorsubstrate 21 under the gate electrodes SG1 and SG2 between SG1 and SG2by oblique ion implantation to form the diffusion layer 28C. Morespecifically, the diffusion layer 28C is formed such that a p-typeimpurity, for example, boron ions are implanted into the semiconductorsubstrate surface by ion implantation in a direction inclined by apredetermined angle with respect to a direction vertical to thesemiconductor substrate surface. In this case, since space (L1) betweenSG1 and SG2>space (L2) between MG and SG1 is satisfied, boron ions areimplanted into the semiconductor substrate 21 between SG1 and SG2.However, boron ions are implanted into the semiconductor substrate 21between MG and SG1 because the boron ions are blocked by the sidesurfaces of the gate electrode MG and selection gate electrode SG1. Inother words, the oblique ion implantation of boron ions is performed atsuch a predetermined angle that the boron ions are implanted into onlyportions under the gate electrodes SG1 and SG2 between SG1 and SG2 andare not implanted into portions under the gate electrodes MG and SG1between MG and SG1.

In this manner, when the source diffusion layer and the drain diffusionlayer of selection gate electrode SG1 are made asymmetrical, defectivewriting (erroneous writing) caused by GIDL (Gate Induced Drain Leakage)in data writing can be reduced while improving cut-off characteristics.

As shown in FIG. 6 a, the TEOS films 30 between MG and SG1 and betweenSG1 and SG2 are removed by using the resist 40 as a mask. In this case,since the TEOS film 30 has film quality different from that of the HTOfilm 29, an etching selectivity to the HTO film 29 can be increased tosome extent. For this reason, only the TEOS film 30 can be etchedwithout removing the HTO film 29. As a result, the sidewall insulatingfilms of the selection gate electrodes SG1 and SG2 of the selection gatetransistor can be reduced in thickness by the film thickness of the TEOSfilm 30.

In the step of removing the TEOS film 30, a step may be formed on aboundary portion of the resist 40, i.e., the HTO film 29 formed on anupper surface of the gate electrode MG adjacent to selection gateelectrode SG1.

Thereafter, as shown in FIG. 6B, the resist 40 is removed, a thirdinsulating film, for example, the TEOS film 31 is deposited by CVD tocover the plurality of first gate electrodes MG and the selection gateelectrodes SG1 and SG2. More specifically, the TEOS film 31 is depositedon a major surface of the semiconductor substrate 21. In this case, theTEOS film 31 is formed to have such a film thickness that the TEOS film31 does not completely bury a gap between the gate electrode MG andselection gate electrode SG1 and a gap between the selection gateelectrodes SG1 and SG2. As shown in FIG. 2, the TEOS film 31 is formedon side surfaces of the selection gate electrodes SG1 and SG2 and a sidesurface of the gate electrode MG between MG and SG1 by anisotropicetching, for example, reactive ion etching (RIE).

As needed to reduce the bit line contact resistance, the diffusion layer28D having an impurity concentration higher than that of the diffusionlayer 28B is formed in a surface region of the diffusion layer 28B.Thereafter, an interlayer insulating film (not shown) is deposited onthe major surface of the semiconductor substrate 21, and then, a bitline contact electrode 6 is formed on the fourth diffusion layer 28Dbetween SG1 and SG2.

In this case, since the TEOS film 30 is removed, the insulating filmsformed on the side surfaces of the selection gate electrodes SG1 and SG2reduce in thickness. For this reason, the bit line contact electrode 6can be prevented from being in contact with the selection gateelectrodes SG1 and SG2. When a contact resistance has no problem, thediffusion layer 28D need not be formed, and the bit line contactelectrode 6 may be formed on the diffusion layer 28B.

With the above manufacturing steps, compensation for halo ionimplantation which densely implants ions into the diffusion layersbetween the gate electrode MG of the memory cell and selection gateelectrode SG1 of the selection gate transistor (between MG and SG1) andbetween the selection gate electrodes SG1 and SG2 of the selection gatetransistor can be performed.

Sidewall insulating films of the selection gate electrodes SG1 and SG2of the selection gate transistor can be reduced, and a chip area can beprevented from increasing.

Second Embodiment

A NAND flash memory according to a second embodiment of the presentinvention will be described below. The same reference numbers as in theconfiguration of the first embodiment denote the same parts in theconfiguration of the second embodiment, and a description thereof willbe omitted. In the first embodiment, a structure of a memory cell arrayin a NAND flash memory is described in the first embodiment. However, inthe second embodiment, in addition to the memory cell array, a structureof a peripheral transistor included in a peripheral circuit formed on aperipheral portion on the same semiconductor substrate as that of thememory cell array and a method of manufacturing the peripheraltransistor is described.

FIG. 7 is sectional views showing a structure of a NAND flash memoryaccording to the second embodiment, (a) shown in FIG. 7 shows a memorycell portion in which a memory cell array is formed, and (b) shown inFIG. 7 shows a peripheral portion in which a peripheral transistor isformed.

The memory cell portion shown in (a) of FIG. 7 has the same structure asthat shown in FIG. 2. On the semiconductor substrate 21, the gateelectrodes of memory cell transistors and selection gate electrodes SG1and SG2 of a section gate transistor are formed. The bit line contactelectrode 6 is formed between SG1 and SG2.

In the peripheral transistor of the peripheral portion, as shown in (b)of FIG. 7, the gate insulating film 22 is formed on the semiconductorsubstrate 21, and a gate electrode PG is formed on the gate insulatingfilm 22. In semiconductor substrates on both sides of the gate electrodePG, source and drain diffusion layers 32 are formed, respectively.

On a side surface of the gate electrode PG, a first insulating film, forexample, the HTO film 29 is formed. On the HTO film 29 on the sidesurface of the gate electrode PG, the second insulating film, forexample, the TEOS film 30 is formed. Furthermore, on the TEOS film 30 onthe side surface of the gate electrode PG, the TEOS film 31 is formed. Asidewall insulating film is formed by the HTO film 29, the TEOS film 30,and the TEOS film 31.

The sidewall insulating film formed on the side surface of the gateelectrode PG of the peripheral transistor is formed to have a filmthickness which is larger than film thicknesses of the sidewallinsulting films of the selection gate electrodes SG1 and SG2 of theselection gate transistor and a film thickness of the sidewallinsulating film of the memory cell between the gate electrode MG andselection gate electrode SG1 by the film thickness of the TEOS film 30.The diffusion layer is formed in the semiconductor substrate 21 tosandwich the gate electrode PG.

The diffusion layer 32 has a so-called LDD structure and is constitutedby an n-type diffusion layer 32A and an n⁺-type diffusion layer 32Bhaving an impurity concentration higher than that of the n-typediffusion layer 32A. The n-type diffusion layer 32A extends from aportion near an end of the gate electrode PG in a direction away fromthe gate electrode PG. The n⁺-type diffusion layer 32B extends from aportion near an end of the TEOS film 31 in a direction away from thegate electrode PG.

For this reason, the n⁺-type diffusion layer 32B having the LDDstructure can be far apart from the end of the gate electrode PG. Morespecifically, in comparison with a case in which an LDD structure isformed by using a sidewall insulating film (HTO film 29 and TEOS film31) of the selection gate transistor, the n⁺-type diffusion layer 32Bhaving the LDD structure can be made farther away from the end of thegate electrode PG. As a result, an inter-source-drain withstand voltageof the peripheral transistor can be improved.

In particular, the drain diffusion layer 32 can be applied to ahigh-withstand-voltage transistor which controls a voltage of 20 V ormore applied across a source and a drain. In this case, the filmthickness of the gate insulating film 22 of the peripheral transistor islarger than film thicknesses of gate insulating films of a memory celltransistor and a selection gate transistor.

The structure of the drain diffusion layer 32 is not limited to the LDDstructure. The drain diffusion layer 32 may employ a DDD structure. Then-type diffusion layer 32A and the n⁺-type diffusion layer 32B can bereplaced with p⁻-type diffusion layer and a p⁺-type diffusion layer,respectively. On the other hand, when the bit line contact electrode 6is brought into contact with the sidewall insulating film of selectiongate electrode SG1 by misalignment in lithography, the bit line contactelectrode 6 decreases in diameter by a size corresponding to thecontact, and a contact resistance disadvantageously increases.Furthermore, a chip area can be reduced by a size corresponding to areduced film thickness of the sidewall insulating film.

According to the second embodiment having the structure described above,in addition to the effect held by the first embodiment, the sidewallinsulating film of the selection gate transistor can be reduced, and thechip area can be reduced. At the same time, since the sidewallinsulating film of the peripheral transistor is formed to have a filmthickness larger than a film thickness of the sidewall insulating filmof the selection gate transistor, the characteristics of the peripheraltransistor can be improved.

A method of manufacturing a NAND flash memory according to the secondembodiment will be described below.

FIGS. 8, 9A and 9B are sectional views showing a method of manufacturinga NAND flash memory according to the second embodiment, (a) and (b)shown in FIG. 8 show the same step, (a) and (b) shown in FIG. 9A showthe same step, and (a) and (b) shown in FIG. 9B show the same step.

The structure shown in (a) of FIG. 8 is the same structure as that shownin FIG. 5. A method of manufacturing the structure is the same as thatin FIG. 5. In the steps of forming the gate electrode MG and theselection gate electrodes SG1 and SG2 shown in FIG. 3, also in theperipheral portion, the gate electrode PG is formed on the semiconductorsubstrate 21. Subsequently, in step of forming the diffusion layers 26B,27B and 28B, also in the peripheral portion, the n-type diffusion layer32A is formed in the semiconductor substrates 21 on both the sides ofthe gate electrode PG by using the gate electrode PG as a mask.

Thereafter, as shown in (a) of FIG. 8, in the step of forming the HTOfilm 29 and the TEOS film 30 on a major surface of the semiconductorsubstrate 21, also in the peripheral portion shown in (b) of FIG. 8, theHTO film 29 and the TEOS film 30 are formed on a major surface of thesemiconductor substrate 21 to cover the gate electrode PG. Subsequently,in the step of forming the resist 40 in the memory cell portion, theupper surface of the TEOS film 30 is covered with the resist 40 in theperipheral portion. Furthermore, phosphorous ions and boron ions areimplanted in the memory cell portion. However, since the peripheralportion is covered with the resist 40, the ion implantation is notperformed.

In the memory cell portion shown in (a) of FIG. 9A, the TEOS films 30between MG and SG1 and between SG1 and SG2 are removed by using theresist 40 as a mask. In this step, in the peripheral portion shown in(b) of FIG. 9A, since the TEOS film 30 is covered with the resist 40,the TEOS film 30 is not removed.

Thereafter, in the memory cell portion shown in (a) of FIG. 9B, theresist 40 is removed, and a third insulating film, for example, the TEOSfilm 31 is deposited by a CVD to cover the plurality of gate electrodesMG and the selection gate electrodes SG1 and SG2. In this step, also inthe peripheral portion shown in (b) of FIG. 9B, the TEOS film 31 isdeposited to cover the gate electrode PG. More specifically, the TEOSfilm 31 is deposited on a major surface of the semiconductor substrate21. In this case, the TEOS film 31 is formed to have such a filmthickness that the TEOS film 31 does not completely bury a gap betweenthe gate electrode MG and selection gate electrode SG1 and a gap betweenthe selection gate electrodes SG1 and SG2.

Subsequently, in the memory cell portion shown in (a) of FIG. 7, byanisotropic etching, for example, RIE, the TEOS films 31 are left onside surfaces of the selection gate electrodes SG1 and SG2 and a sidesurface of the gate electrode MG between MG and SG1. In this step, alsoin the peripheral portion shown in (b) of FIG. 7, the TEOS film 31 isleft on a side surface of the gate electrode PG by anisotropic etching.The HTO film 29 and the TEOS film 30 which are not covered with the TEOSfilm 31 formed on the side surface of the gate electrode MG are removedby this step.

Thereafter, in the peripheral portion shown in (b) of FIG. 7, forexample, arsenic ions are implanted by ion implantation by using thegate electrode PG and the TEOS film 31 as masks to form the n⁺-typediffusion layer 32B. In the memory cell portion, as in the firstembodiment, the diffusion layer 28D is formed. Thereafter an interlayerinsulating film (not shown) is deposited, and then the bit line contactelectrode 6 is formed on the diffusion layer 28D.

With the steps described above, in addition to the memory cell arrayaccording to the first embodiment, a peripheral transistor can be formedin the peripheral portion. In the second embodiment, the sidewallinsulating film of the peripheral transistor can be formed to have afilm thickness which is larger than that of the sidewall insulating filmof the selection gate transistor by the film thickness of the TEOS film30. For this reason, a high-withstand-voltage transistor which controlsa voltage of, for example, about 20 V can be easily manufactured.

In the embodiment according to the present invention, the sidewall ofthe gate electrode is constituted by two layers, i.e., the HTO filmhaving a low etching rate and the TEOS film having a high etching rate,and the TEOS film of the sidewall of the selection gate electrode ispartially removed, the sidewall insulating film of the selection gatetransistor can be reduced in thickness. At this time, a film thicknessof a sidewall insulating film of a peripheral MOS transistorconstituting the peripheral circuit does not decrease. When boron ionsare obliquely implanted before one TEOS film of the sidewall of theselection gate electrode is removed, boron ions can be prevented frombeing implanted into a space between the selection gate transistor andthe memory cell, the space being larger than a space between the memorycells. When phosphorous ions are implanted into a semiconductorsubstrate surface, compensation for halo ion implantation which denselyimplants ions into a large space between the selection gate transistorand the memory cell can be performed.

The embodiment of the present invention provides a semiconductor memorydevice which can prevent a threshold voltage of a memory cell arrangedadjacent to a selection gate transistor from rising and can reduce achip area and a method of manufacturing the same.

The embodiments described above cannot merely be independently executed,but also can be executed by being combined to each other. In each of theembodiments, the n-type memory cell transistor and the n-type selectiongate transistor are exemplified. However, a p-type memory celltransistor and an n-type selection gate transistor may be performed. Inthis case, the n-type transistor and the p-type transistor described inthe embodiments may be replaced with each other.

Furthermore, each of the embodiments described above includes inventionsin various phases. The inventions in the various phases can also beextracted by appropriately combining a plurality of constituent elementsdisclosed in the embodiments.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-7. (canceled)
 8. A method of manufacturing a semiconductor memorydevice comprising: forming a plurality of first gate electrodes of aplurality of memory cell transistors, a second gate electrode of a firstselection gate transistor, and a third gate electrode of a secondselection gate transistor on a semiconductor substrate, the plurality offirst gate electrodes being arranged at predetermined spaces in serieswith each other, the second gate electrode being arranged at one end ofthe plurality of first gate electrodes arranged in series with eachother, and the third gate electrode being arranged adjacent to thesecond gate electrode; covering the plurality of first gate electrodes,the second gate electrode, and the third gate electrode with a firstinsulating film, and forming the first insulating film on thesemiconductor substrate; forming a second insulating film on the firstinsulating film; forming a mask material on the second insulating filmto cover a gap between the first gate electrodes and to form a openingbetween the first gate electrode and the second gate electrode andbetween the second gate electrode and the third gate electrode; afterthe mask material is formed, removing the second insulating filmsbetween the first gate electrode and the second gate electrode andbetween the second gate electrode and the third gate electrode; afterthe mask material is removed, covering the plurality of first gateelectrodes, the second gate electrode, and the third gate electrode witha third insulating film, and forming the third insulating film on thesemiconductor substrate; and etching the third insulating film byanisotropic etching to form sidewall insulating films on a side surfaceof the first gate electrode between the first gate electrode and thesecond gate electrode and on side surfaces of the second and third gateelectrodes.
 9. The method of manufacturing a semiconductor memory deviceaccording to claim 8, further comprising, after the plurality of firstgate electrodes, the second gate electrode, and the third gate electrodeare formed, forming first diffusion layers of a first conductivity typein the semiconductor substrate between the plurality of first gateelectrodes, the semiconductor substrate between the first gate electrodeand the second gate electrode, and the semiconductor substrate betweenthe second gate electrode and the third gate electrode.
 10. The methodof manufacturing a semiconductor memory device according to claim 9,further comprising, after the first diffusion layers are formed, formingsecond diffusion layers of a second conductivity type in thesemiconductor substrate under the first diffusion layers.
 11. The methodof manufacturing a semiconductor memory device according to claim 10,further comprising, after the mask material is formed, implantingimpurity ions of the first conductivity type by ion implantation intothe second diffusion layer between the first gate electrode and thesecond gate electrode and the second diffusion layer between the secondgate electrode and the third gate electrode.
 12. The method ofmanufacturing a semiconductor memory device according to claim 11,further comprising, after the mask material is formed, forming thirddiffusion layers of the second conductivity type at both ends of thesecond diffusion layer between the second gate electrode and the thirdgate electrode, the third diffusion layers being formed by ionimplantation in a direction inclined at a predetermined angle withrespect to a direction vertical to a semiconductor substrate surface.13. A method of manufacturing a semiconductor memory device comprising:forming a plurality of first gate electrodes of a plurality of memorycell transistors, a second gate electrode of a first selection gatetransistor, a third gate electrode of a second selection gatetransistor, and a fourth gate electrode of a peripheral transistor on asemiconductor substrate, the plurality of first gate electrodes beingarranged at predetermined spaces in series with each other, the secondgate electrode being arranged at one end of the plurality of first gateelectrodes arranged in series with each other, and the third gateelectrode being arranged adjacent to the second gate electrode; coveringthe plurality of first gate electrodes, the second gate electrode, thethird gate electrode, and the fourth gate electrode with a firstinsulating film, and forming the first insulating film on thesemiconductor substrate; forming a second insulating film on the firstinsulating film; forming a mask material on the second insulating filmto cover a gap between the first gate electrodes and the fourth gateelectrode and to form a opening between the first gate electrode and thesecond gate electrode and between the second gate electrode and thethird gate electrode; after the mask material is formed, removing thesecond insulating films between the first gate electrode and the secondgate electrode and between the second gate electrode and the third gateelectrode; after the mask material is removed, covering the plurality offirst gate electrodes, the second gate electrode, the third gateelectrode, and the fourth gate electrode with a third insulating film,and forming the third insulating film on the semiconductor substrate;and etching the third insulating film by anisotropic etching to formfirst sidewall insulating films on a side surface of the first gateelectrode between the first gate electrode and the second gate electrodeand on side surfaces of the second and the third gate electrodes and toform a second sidewall insulating film on a side surface of the fourthgate electrode.
 14. The method of manufacturing a semiconductor memorydevice according to claim 13, further comprising, after the plurality offirst gate electrode, the second gate electrode, the third gateelectrode, and the fourth gate electrode are formed, forming firstdiffusion layers of a first conductivity type in the semiconductorsubstrate between the plurality of first gate electrodes, thesemiconductor substrate between the first gate electrode and the secondgate electrode, and the semiconductor substrate between the second gateelectrode and the third gate electrode.
 15. The method of manufacturinga semiconductor memory device according to claim 14, further comprising,after the first diffusion layers are formed, forming second diffusionlayers of a second conductivity type in the semiconductor substrateunder the first diffusion layers.
 16. The method of manufacturing asemiconductor memory device according to claim 15, further comprising,after the mask material is formed, implanting impurity ions of the firstconductivity type by ion implantation into the second diffusion layerbetween the first gate electrode and the second gate electrode and thesecond diffusion layer between the second gate electrode and the thirdgate electrode.
 17. The method of manufacturing a semiconductor memorydevice according to claim 16, further comprising, after the maskmaterial is formed, forming third diffusion layers of the secondconductivity type at both ends of the second diffusion layer between thesecond gate electrode and the third gate electrode, the third diffusionlayers being formed by ion implantation in a direction inclined at apredetermined angle with respect to a direction vertical to asemiconductor substrate surface.